Low Power VLSI Circuits Design Strategies and Methodologies: A Literature Review

Researchers stare at the design of low power devices as they are ruling the today's electronics industries. In VLSI circuits, power dissipation is a critical design parameter as it plays a vital role in the performance estimation of the battery operated devices particularly used in biomedical applications. The decrease in chip size and increase in chip density and complexity escalate the difficulty in designing higher performance low power consuming system on a chip. Further, overall power management on a chip is becoming a big challenge below 100 nm node because of its increased design complexity. Besides, leakage current also plays a vital role in Power management of low power VLSI devices. In sub-micron technologies, leakage and dynamic power consumption is becoming an essential design parameter as it is dissipating a considerable portion of the total power consumption. To increase the battery life of portable devices, leakage and dynamic power reduction is emerging as a primary goal of the VLSI circuit design. This paper provides an insight about the various methodologies, strategies and power management techniques to be used for the design of low power circuit based systems.