A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders

被引:36
|
作者
Pashaeifar, Masoud [1 ]
Kamal, Mehdi [1 ]
Afzali-Kusha, Ali [1 ,2 ]
Pedram, Massoud [3 ]
机构
[1] Univ Tehran, Sch Elect & Comp Engn, Tehran 1439957131, Iran
[2] Inst Res Fundamental Sci IPM, Sch Comp Sci, Tehran 1953833511, Iran
[3] Univ Southern Calif, Dept Elect Engn, Los Angeles, CA 90089 USA
关键词
Approximation noise; analytical quality estimation; approximate computing; optimization; low power approximate adders; digital signal processing; ERROR-TOLERANT ADDER;
D O I
10.1109/TCSI.2018.2856757
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we present a framework for analytically estimating the output quality of common digital signal processing (DSP) blocks that utilize approximate adders. The framework is based on considering the error of approximate adders as an additive noise (approximation noise) that disturbs the output of the DSP block in question. A signal processing theoretical modeling approach for describing the power of the approximation noise which is the integral of error spectral density over the bandwidth, is developed. The output qualities of DSP blocks, such as finite impulse response filter, discrete cosine transform, and fast Fourier transform, which utilize approximate adders, are thus estimated. The accuracy of the proposed framework is evaluated by comparing mathematical model predictions to simulation results by using the signal-to-noise ratio (SNR) metric. The inaccuracy of the SNRs predicted by the framework was, on average, less than 2.5dB compared with that obtained from simulations. Therefore, a mathematical optimization approach based on Lagrange Multipliers for optimizing design parameters is also presented. The optimization is realized by choosing a proper configuration of the target block, such as determining the data width of the inexact computation part for each approximate adder in the design.
引用
收藏
页码:327 / 340
页数:14
相关论文
共 50 条
  • [21] Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing
    Yang, Wu
    Thapliyal, Himanshu
    2020 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2020), 2020, : 312 - 315
  • [22] An Architectural Framework for Low-Power IoT Applications
    Yelmarthi, Kumar
    Abdelgawad, Ahmed
    Khattab, Ahmed
    2016 28TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (ICM 2016), 2016, : 373 - 376
  • [23] Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders
    Dharmaraj, Celia
    Vasudevan, Vinita
    Chandrachoodan, Nitin
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2021, 20 (02)
  • [24] Low Power, High Speed Error Tolerant Multiplier Using Approximate Adders
    Reddy, Manikantta K.
    Kumar, Nithin Y. B.
    Sharma, Dheeraj
    Vasantha, M. H.
    2015 19TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2015,
  • [25] Low-Power Ternary Multiplication Using Approximate Computing
    Nagesh, Gode
    Sumalatha, Madipalli
    2024 INTERNATIONAL CONFERENCE ON SOCIAL AND SUSTAINABLE INNOVATIONS IN TECHNOLOGY AND ENGINEERING, SASI-ITE 2024, 2024, : 208 - 212
  • [26] Low-power digital filtering using approximate processing
    Ludwig, JT
    Nawab, SH
    Chandrakasan, AP
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (03) : 395 - 400
  • [27] Low-Power Ternary Multiplication Using Approximate Computing
    Kim, Sunmean
    Kang, Yesung
    Baek, Seunghan
    Choi, Youngchang
    Kang, Seokhyeong
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68 (08) : 2947 - 2951
  • [28] Robust motion estimation on a low-power multi-core DSP
    Igual, Francisco D.
    Botella, Guillermo
    Garcia, Carlos
    Prieto, Manuel
    Tirado, Francisco
    EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING, 2013,
  • [29] Robust motion estimation on a low-power multi-core DSP
    Francisco D. Igual
    Guillermo Botella
    Carlos García
    Manuel Prieto
    Francisco Tirado
    EURASIP Journal on Advances in Signal Processing, 2013
  • [30] A low-power embedded RISC microprocessor with an integrated DSP for mobile applications
    Yamada, T
    Ishikawa, M
    Ogata, Y
    Tsunoda, T
    Irita, T
    Tamaki, S
    Nishiyama, K
    Kamei, T
    Tatezawa, K
    Arakawa, F
    Nakazawa, T
    Hattori, T
    Uchiyama, K
    IEICE TRANSACTIONS ON ELECTRONICS, 2002, E85C (02) : 253 - 262