Fast Modeling Technique for Nano Scale CMOS Inverter and Propagation Delay Estimation

被引：0

作者：

Rjoub, Abdoul ^{[1
,2
]}

Ahmad, Areej ^{[1
,2
]}

机构：

[1] Jordan Univ Sci & Technol, Comp Engn Dept, POB 3030, Irbid 22110, Jordan

[2] Purdue Univ, ECE Dept, W Lafayette, IN 47907 USA

来源：

2014 24TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) | 2014年

关键词：

Channel Length Modulation; Drain-Induced Barrier Lowering(DIBL); Mobility Degradation; Propagation Delay(Pd); Unit Step Waveform; Velocity Saturation;

D O I：

暂无

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

this paper proposes a new approach for designing the output waveform nanoscale CMOS inverter using the unit step input. The output waveform is obtained by solving the corresponding differential equations of the circuit. Various phenomena due to Short Channel Effects are included in the equation to achieve more accurate model. Based on this model, the propagation delay time for the input is estimated and used to get the ramp input propagation delay based on its deviation with step input propagation delay. This method is used to avoid the overhead in the CPU execution time during simulation process for huge number of inverters. The evaluations of the proposed model results give very good agreement when compared with BSIM4 level 54 model using HSPICE.

引用

页数：4

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