Integration technologies for scalable high density MRAM

被引：0

作者：

Park, JH ^{[1
]}

Jeong, WC ^{[1
]}

Oh, JH ^{[1
]}

Jeong, CW ^{[1
]}

Shin, JM ^{[1
]}

Hwang, YN ^{[1
]}

Ahn, SJ ^{[1
]}

Lee, SH ^{[1
]}

Lee, SY ^{[1
]}

Ryoo, KC ^{[1
]}

Park, J ^{[1
]}

Yang, F ^{[1
]}

Koh, GH ^{[1
]}

Jeong, GT ^{[1
]}

Jeong, HS ^{[1
]}

Kim, K ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Semicond R&D Div, Adv Technol Dev, Yongin 449711, Gyeonggi Do, South Korea

来源：

2005 IEEE VLSI-TSA International Symposium on VLSI Technology (VLSI-TSA-TECH), Proceedings of Technical Papers | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We investigate the key factors for scalable high density MRAM. Specifically we examine problems such as large switching field, small sensing margin and writing disturbance following a decrease in size. We demonstrate these problems and suggest several solutions for realizing high density MRAM.

引用

页码：39 / 40

页数：2

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