The design of an FPGA-based MIMO receiver: Algorithmic and architectural interactions

A research team at Brigham Young University is currently developing a high-performance, FPGA-based demodulator for detecting a space-time coded signal. The project timeline required that the algorithm be concurrently developed, to a certain extent, with the hardware implementation. Thus, from the outset both algorithm and hardware implementation researchers worked closely together in contrast to the, all too common, three-step development approach (algorithm development, throw-algorithm-over-wall, hardware implementation). In this paper we outline the unique characteristics of the System and then discuss the interaction between algorithm design and architectural implementation. In particular, we focus on two blocks from the system: the carrier frequency offset estimation block and the pilot detector block and show their evolution from their original mathematical formulations to equivalent but greatly simplified hardware implementations.