A Design of FPGA-based DSRC Receiver

被引：0

作者：

Li, Xiang ^{[1
]}

Wang, Chao ^{[1
]}

Liu, Fuqiang ^{[1
]}

Liu, Fen ^{[2
]}

He, Changwei ^{[2
]}

Lv, Chenghao ^{[2
]}

Yin, Wei ^{[2
]}

Zou, Qingquan ^{[2
]}

机构：

[1] Tongji Univ, Sch Elect & Informat Engn, Shanghai, Peoples R China

[2] SAIC Motor Corp Ltd, Adv Technol Dev Dept, Shanghai, Peoples R China

来源：

PROCEEDINGS OF THE 2015 10TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND NETWORKING IN CHINA CHINACOM 2015 | 2015年

关键词：

Dedicated short range communications (DSRC); ad hoc network; test-bed; wireless transceiver; TIMING SYNCHRONIZATION; CHANNEL ESTIMATION; OFDM SYSTEMS; FREQUENCY;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The Dedicated Short Range Communications (DSRC)-based vehicular communications suffer from highly dynamic outdoor environments, which cannot be characterized correctly and accurately by computer-based simulations. Evaluating new algorithms and schemes in real outdoor environments highlights the need for an easy-to-use DSRC test-bed. In this paper, a DSRC receiver is designed and implemented by using the Field Programmable Gate Array (FPGA) platform. Several related transceiver algorithms for the signal detection, frame synchronization and channel estimation are reviewed and analyzed by combining the IEEE 802.11p standard with the vehicular communication environments, and a set of proper algorithms are adopted to enhance the system performance. The implementation of the proposed receiver is further optimized according to the characteristics of FPGA. The implementation result agrees that a significant reduction on the hardware resource usage is achieved by the proposed design.

引用

页码：585 / 589

页数：5

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