Static test compaction for IDDQ testing of sequential circuits

被引：0
|
作者：
Higami, Y [1 ]
Saluja, KK [1 ]
Kinoshita, K [1 ]
机构：
[1] Ehime Univ, Fac Engn, Matsuyama, Ehime 790, Japan
来源：
1998 IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, PROCEEDINGS | 1998年
关键词：
D O I：
10.1109/IDDQ.1998.730725
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a static test compaction method for IDDQ testing of sequential circuits. Target faults are bridging faults between arbitrary pair of nodes including internal nodes, signal lines, VDD and GND. In the proposed method, test subsequences are removed and replaced with shorter subsequences.
引用
收藏
页码：9 / 13
页数：5
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