Static compaction of test sequences for synchronous sequential circuits

The cost of testing a VLSI circuit is greatly affected by the length of its test sequence. Compaction techniques are often used to reduce the test sequence length. In this paper we propose a new test sequence compaction procedure for synchronous sequential circuits aimed at improving the level of compaction. The procedure belongs to the class of procedures that omit test vectors from a given test sequence in order to reduce its length without reducing the fault coverage. We apply the proposed techniques to the compaction of test sequences for benchmark circuits generated by our previous test generation procedure. The results show that the test sequences can be significantly compacted The compacted sequences thus have shorter test application times and smaller memory requirements. As a by-product, the fault coverage is sometimes increased as well. In addition, the procedure can also be applied to other test generation procedures.