Implementation of flight control computer hardware using the C6701 processor

被引：0
|
作者：
Kwon, Jong-Kwang [1 ]
Byun, Jin-Ku [1 ]
Ahn, Jong-Min [1 ]
Ko, Joon-Soo [1 ]
Lee, Dae-Yearl [1 ]
Kim, Whan-Woo [2 ]
机构：
[1] Agcy Def Dev, Dep Aircraft, Taejon 305600, South Korea
[2] Chung Nam Natl Univ, Dep Elect Eng, Daejeon 305764, South Korea
来源：
NEW ADVANCES IN SIMULATION, MODELLING AND OPTIMIZATION (SMO '07) | 2007年
关键词：
digital flight control computer (DFLCC); SMJ320C6701; Flying Test Bed (FTB); Korean Supersonic Aircraft (KSA); flight control system (FCS); central processing unit (CPU); input output processor (IOP); rapid prototyping (RP);
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Flying Test Bed (FTB) program is to establish the in-house capability of digital flight control computer (DFLCC) development which will be installed on the existing Korean Supersonic Aircraft (KSA). A hardware manufacturing technology of DFLCC mainly lies in constitution and layout of central processing unit (CPU), and input output processor (IOP) board which includes core processor, with those of other boards. The FTB DFLCC has triplex digital redundancy architecture. We use to DFLCC rapid prototyping (RP) to help the participants perform design review and function analysis easily. In this paper, we present the establishment and implementation of FTB DFLCC hardware using the SMJ320C6701 processor and RP. Also, channel valid logic and cross channel data link (CCDL) are described for redundancy management.
引用
收藏
页码：352 / +
页数：2
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