A low dynamic power and low leakage power CMOS square-root circuit

被引：0
|
作者：
Enomoto, T [1 ]
Kobayashi, N [1 ]
机构：
[1] Chuo Univ, Grad Sch Sci & Engn, Bunkyo Ku, Tokyo 1120881, Japan
来源：
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年
关键词：
D O I：
10.1109/ISCAS.2005.1464928
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
To drastically reduce the dynamic power (P(AT)) and the leakage power (P(ST)), while to increase operating speed of a CMOS square-root (SR) circuit, a new SR algorithm and a self-controllable-voltage-level (SVL) circuit consisting of a single CMOS switch has been developed. They can drastically decrease not only a number of gate count (G(c)) of the critical path and a number of total logic gates (G(c)), but also considerably reduce the leakage power. G(c) and G of the new 8-bit, 0.16-mu m CMOS SR circuit were greatly reduced to 30 and 97, which were 50.0% and 51.3% of those of a conventional SR circuit, respectively. Thus, the maximum operating frequency (f(c)) of the new SR circuit at supply voltage (V(DD)) of 1.5 V was 581 MHz that was 1.62 times faster than that (358 MHz) of the conventional SR circuit. PAT of the new SR circuit at f(c) of 200 MHz and VDD of 1.5 V was reduced to 309 mu W, which was 54.3% of that (569 mu W) of a conventional SR circuit. PST of the new SR circuit was only 8.8 nW which was 1.36% that (647nW) of the conventional SR circuit.
引用
收藏
页码：1678 / 1681
页数：4
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