LDPC Decoder Implementation Using FPGA

被引：0
|
作者：
Kiaee, Mahdie [1 ]
Gharaee, Hossein [2 ]
Mohammadzadeh, Naser [1 ]
机构：
[1] Shahed Univ, Dept Comp Engn, Tehran, Iran
[2] Iran Telecom Res Ctr, Tehran, Iran
来源：
2016 8TH INTERNATIONAL SYMPOSIUM ON TELECOMMUNICATIONS (IST) | 2016年
关键词：
LDPC decoder; hardware implementation; FPGA; time scheduling; TPMP algorithm; EFFICIENT DECODER; ARCHITECTURES; DESIGN; AREA;
D O I：
暂无
中图分类号：
TN [电子技术、通信技术];
学科分类号：
0809 ;
摘要：
This paper presents a partial-parallel LDPC decoder based on sum-product algorithm with high throughput. The hardware implementation of decoder considers design issues with respect to FPGA and time scheduling is proposed based on modified TPMP1 algorithm in order to reduce the number of clock cycles, hardware resources and power. The decoder is implemented for a code length of 672 whit rate of 3/4, maximum throughput of 3360 Mbps in maximum frequency of 280 MHz and provides power of 150 mW.
引用
收藏
页码：167 / 173
页数：7
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