LDPC Decoder Implementation Using FPGA

被引：0

作者：

Kiaee, Mahdie ^{[1
]}

Gharaee, Hossein ^{[2
]}

Mohammadzadeh, Naser ^{[1
]}

机构：

[1] Shahed Univ, Dept Comp Engn, Tehran, Iran

[2] Iran Telecom Res Ctr, Tehran, Iran

来源：

2016 8TH INTERNATIONAL SYMPOSIUM ON TELECOMMUNICATIONS (IST) | 2016年

关键词：

LDPC decoder; hardware implementation; FPGA; time scheduling; TPMP algorithm; EFFICIENT DECODER; ARCHITECTURES; DESIGN; AREA;

D O I：

暂无

中图分类号：

TN [电子技术、通信技术];

学科分类号：

0809 ;

摘要：

This paper presents a partial-parallel LDPC decoder based on sum-product algorithm with high throughput. The hardware implementation of decoder considers design issues with respect to FPGA and time scheduling is proposed based on modified TPMP1 algorithm in order to reduce the number of clock cycles, hardware resources and power. The decoder is implemented for a code length of 672 whit rate of 3/4, maximum throughput of 3360 Mbps in maximum frequency of 280 MHz and provides power of 150 mW.

引用

页码：167 / 173

页数：7

共 50 条

[21] Research on the Implementation of QC-LDPC Decoder Based on FPGA
Zhang, Yang
Wang, Xiumin
Lou, Xizhong
Yang, Shihua
Chen, Haowei
ICMS2010: PROCEEDINGS OF THE THIRD INTERNATIONAL CONFERENCE ON MODELLING AND SIMULATION, VOL 6: MODELLING & SIMULATION INDUSTRIAL ENGINEERING & MANAGEMENT, 2010, : 274 - 277
[22] High Performance LDPC Decoder design using FPGA
Pawankar, Shraddha
Mohota, Nilesh
2019 9TH INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY: SIGNAL AND INFORMATION PROCESSING (ICETET-SIP-19), 2019,
[23] A FPGA design and implementation of low-complexity decoder for LDPC code
Shi, Shao-Bo
Qi, Yue
Wang, Qin
Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences, 2013, 40 (11 SUPPL.): : 18 - 22
[24] Implementation of QC-LDPC Decoder Based on FPGA for FSO System
Qiong, Yan Guo
Hua, Zhou Mao
MECHANICAL COMPONENTS AND CONTROL ENGINEERING III, 2014, 668-669 : 1269 - +
[25] Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder
Spagnol, C
Marnane, W
Popovici, E
Proceedings of the 2005 European Conference on Circuit Theory and Design, Vol 1, 2005, : 289 - 292
[26] FPGA implementation of a high-throughput memory-efficient LDPC decoder
School of Electronic Engineering, Xidian Univ., Xi'an 710071, China
不详
Xi'an Dianzi Keji Daxue Xuebao, 2008, 3 (427-432):
[27] FPGA Implementation of High Performance QC-LDPC Decoder for Optical Communications
Zou, Ding
Djordjevic, Ivan B.
OPTICAL METRO NETWORKS AND SHORT-HAUL SYSTEMS VII, 2015, 9388
[28] FPGA implementation of high-throughput irregular structured LDPC encoder and decoder
Wang, Wenjun
Zhu, Xiaoxuan
Kang, Guixia
Zhang, Ping
Shuju Caiji Yu Chuli/Journal of Data Acquisition and Processing, 2008, 23 (SUPPL.): : 113 - 118
[29] Implementation of a flexible LDPC decoder
Masera, Guido
Quaglio, Federico
Vacca, Fabrizio
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (06) : 542 - 546
[30] Poster: FPGA Based Implementation of Overlapped QC-LDPC Decoder with Limited Resources
Xu Dijia
Bie Hongxia
Zheng Jian
Lei Chunyang
2014 9TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND NETWORKING IN CHINA (CHINACOM), 2014, : 652 - 653

← 1 2 3 4 5 →