Value Iteration on Multicore Processors

被引:0
|
作者
Jain, Anuj [1 ]
Sahni, Sartaj [2 ]
机构
[1] Adobe Syst Inc, Lehi, UT 84043 USA
[2] Univ Florida, CISE Dept, Gainesville, FL USA
基金
美国国家科学基金会;
关键词
Reinforcement Learning; Markov Decision Process; Value Iteration; Multicore; Parallelization;
D O I
10.1109/ISSPIT51521.2020.9408773
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Value Iteration (VI) is a powerful, though time consuming, approach to solve reinforcement learning problems modeled as Markov Decision Processes (MDPs). In this paper, we explore strategies to run the sate-of-the-art cache efficient algorithm for VI developed by us [1], [2] on a multicore processor. We demonstrate a speedup of up to 2.59 on a 10-core multiprocessor using 20 threads on popular benchmark data. The speedup for the parallelized portion of the computation is up to 5.89.
引用
收藏
页数:7
相关论文
共 50 条
  • [21] Concurrent FFT computing on multicore processors
    Barhen, J.
    Humble, T.
    Mitra, P.
    Imam, N.
    Schleck, B.
    Kotas, C.
    Traweek, M.
    CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2012, 24 (01): : 29 - 44
  • [22] Parallel evidence propagation on multicore processors
    Xia, Yinglong
    Prasanna, Viktor K.
    JOURNAL OF SUPERCOMPUTING, 2011, 57 (02): : 189 - 202
  • [23] Adaptive Task Scheduling on Multicore Processors
    Nour, Samar
    Mahmoud, Shahira
    Saleh, Mohamed
    INTERNATIONAL CONFERENCE ON ADVANCED MACHINE LEARNING TECHNOLOGIES AND APPLICATIONS (AMLTA2018), 2018, 723 : 575 - 584
  • [24] A review of transactional memory in multicore processors
    Wang X.
    Ji Z.
    Fu C.
    Hu M.
    Information Technology Journal, 2010, 9 (01) : 192 - 200
  • [25] Limitations of Interference Analyses on Multicore Processors
    Mutuel, Laurence
    Jean, Xavier
    Soulat, Romain
    2017 IEEE/AIAA 36TH DIGITAL AVIONICS SYSTEMS CONFERENCE (DASC), 2017,
  • [26] Evaluating the cache architecture of multicore processors
    Tao, Jie
    Kunze, Marcel
    Karl, Wolfgang
    PROCEEDINGS OF THE 16TH EUROMICRO CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING, 2008, : 12 - +
  • [27] ParTejas: A Parallel Simulator for Multicore Processors
    Malhotra, Geetika
    Kalayappan, Rajshekar
    Goel, Seep
    Aggarwal, Pooja
    Sagar, Abhishek
    Sarangi, Smruti R.
    ACM TRANSACTIONS ON MODELING AND COMPUTER SIMULATION, 2017, 27 (03):
  • [28] Performance of OpenMP benchmarks on Multicore processors
    Marowka, Ami
    ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, PROCEEDINGS, 2008, 5022 : 208 - +
  • [29] Chip makers turn to multicore processors
    Geer, D
    COMPUTER, 2005, 38 (05) : 11 - 13
  • [30] Video Coding on Multicore Graphics Processors
    Cheung, Ngai-Man
    Fan, Xiaopeng
    Au, Oscar C.
    Kung, Man-Cheung
    IEEE SIGNAL PROCESSING MAGAZINE, 2010, 27 (02) : 79 - 89