The characteristics of solid phase crystallized (SPC) polycrystalline silicon thin film transistors employing amorphous silicon process

被引：9

作者：

Lee, Won-Kyu ^{[1
,2
]}

Han, Sang-Myeon ^{[1
]}

Choi, Joonhoo ^{[2
]}

Han, Min-Koo ^{[1
]}

机构：

[1] Seoul Natl Univ, Sch Elect Engn, Seoul 151742, South Korea

[2] Samsung Elect Co, LCD Business, Yongin 449711, South Korea

来源：

JOURNAL OF NON-CRYSTALLINE SOLIDS | 2008年 / 354卷 / 19-25期

关键词：

devices; thin film transistors;

D O I：

10.1016/j.jnoncrysol.2007.09.083

中图分类号：

TQ174 [陶瓷工业]; TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

We investigated the electrical properties of polycrystalline silicon (poly-Si) thin film transistors (TFTs) employing field-enhanced solid phase crystallization (FESPC). An n+ amorphous silicon (n+ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal instead of ion doping. By using C-V measurement method, we could explain the diffused phosphorous ions (P+ ions) on the channel surface caused a negatively shifted threshold voltage (V-TH) of -7.81 V at a drain bias of 0.1 V, and stretched out a subthreshold swing (S) of 1.698 V/dec. This process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process and also offers a better uniformity when compared to the conventional laser-crystallized poly-Si TFT process because of non-laser crystallization. (C) 2007 Elsevier B.V. All rights reserved.

引用

页码：2509 / 2512

页数：4

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