Leakage current of unhydrogenated solid phase crystallized silicon thin film transistors

A study of the leakage current in unhydrogenated polycrystalline silicon Thin Film Transistors (TFT) is performed. Active layer and drain and source regions of these TFT's are amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique, and insitu solid-phase crystallized. Gate insulator is an atmospheric chemical vapor deposited SiO2 layer. Different increasing quality silicon films are obtained by varying the deposition pressure. Moreover two processes giving two different performance TFT's types, double layer type and monolayer type, are used. Depending on the Drain-Source voltage V-D, on the Gate-Source voltage V-G, and the material quality, 3 regimes of variation of Drain Current I-D with V-D are highlighted. At low V-G and V-D, I-D linearly increases with V-D, indicating that the current is limited by the transport in the channel material. When V-G increases, I-D-V-D curve shows a square root behavior. Then at high V-G and high V-D, the variation of I-D with V-D becomes more important. The relative importance of these 3 regimes depends on the material quality and the type of process of the TFT's. In high quality TFT's, the second regime dominates. Its importance increases with the material quality. At high V-D and high V-G, the third regime dominates whatever the material quality and the process.