共 50 条
- [21] Post-Silicon Code Coverage Evaluation with Reduced Area Overhead for Functional Verification of SoC 2011 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT), 2011, : 92 - 97
- [22] Bridging Pre-Silicon Verification and Post-Silicon Validation PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 94 - 95
- [23] QED Post-Silicon Validation and Debug Invited Abstract 2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), 2014, : 62 - 62
- [25] ISTA: An Embedded Architecture for Post-silicon Validation in Processors 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 593 - 596
- [26] Dynamic Trace Signal Selection for Post-Silicon Validation 2013 26TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2013 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2013, : 302 - 307
- [27] On bypassing blocking bugs during post-silicon validation PROCEEDINGS OF THE 13TH IEEE EUROPEAN TEST SYMPOSIUM: ETS 2008, 2008, : 69 - 74
- [28] Post-Silicon Validation and Calibration of Hardware Security Primitives 2014 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2014, : 29 - 34
- [29] On-Chip Stimuli Generation for Post-Silicon Validation 2012 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT), 2012, : 108 - 109