CMOS structures suitable for secured hardware

被引：20

作者：

Guilley, S ^{[1
]}

Hoogvorst, P ^{[1
]}

Mathieu, Y ^{[1
]}

Pacalet, R ^{[1
]}

Provost, J ^{[1
]}

机构：

[1] Telecom Paris, GET, CNRS, LTCI,Dept Commun & Elect, F-75634 Paris 13, France

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/DATE.2004.1269113

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.

引用

页码：1414 / 1415

页数：2

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