Utilization-Based Resource Partitioning for Power-Performance Efficiency in SMT Processors

被引:8
|
作者
Wang, Huaping [1 ]
Koren, Israel [1 ]
Krishna, C. Mani [1 ]
机构
[1] Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA
基金
美国国家科学基金会;
关键词
Simultaneous multithreading; resource partitioning; power-performance efficiency;
D O I
10.1109/TPDS.2010.199
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Simultaneous multithreading (SMT) increases processor throughput by allowing parallel execution of several threads. However, fully sharing processor resources may cause resource monopolization by a single thread or other misallocations, resulting in overall performance degradation. Static resource partitioning techniques have been suggested, but are not as effective as dynamic ones since program behavior does change over the course of its execution. In this paper, we propose an Adaptive Resource Partitioning Algorithm (ARPA) that dynamically assigns resources to threads according to changes in thread behavior. ARPA analyzes the resource usage efficiency of each thread in a given time period and assigns more resources to threads which can use them more efficiently. Its purpose is to improve the efficiency of resource utilization, thereby improving overall instruction throughput. Our simulation results on a set of 42 multiprogramming workloads show that ARPA outperforms the traditional fetch policy ICOUNT by 55.8 percent with regard to overall instruction throughput and achieves a 33.8 percent improvement over Static Partitioning. It also outperforms the current best dynamic resource allocation technique, Hill-climbing, by 5.7 percent. Considering fairness accorded to each thread, ARPA attains 43.6, 18.5, and 9.2 percent improvements over ICOUNT, Static Partitioning, and Hill-climbing, respectively, using a common fairness metric. We also explore the energy efficiency of dynamically controlling the number of powered-on reorder buffer entries for ARPA. Compared with ARPA, our energy-aware resource partitioning algorithm achieves 10.6 percent energy savings, while the performance loss is negligible.
引用
收藏
页码:1150 / 1163
页数:14
相关论文
共 50 条
  • [21] VSMT-IO: Improving I/O Performance and Efficiency on SMT Processors in Virtualized Clouds
    Jia, Weiwei
    Shan, Jianchen
    Li, Tsz On
    Shang, Xiaowei
    Cui, Heming
    Ding, Xiaoning
    PROCEEDINGS OF THE 2020 USENIX ANNUAL TECHNICAL CONFERENCE, 2020, : 449 - 463
  • [22] System-Level Power-Performance Efficiency Modeling for Emergent GPU Architectures
    Song, Shuaiwen
    Cameron, Kirk W.
    PROCEEDINGS OF THE 21ST INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT'12), 2012, : 473 - 473
  • [23] Utilization-based grouping efficiency and multi-criteria decision approach in designing of manufacturing cells
    Ghosh, Tamal
    Doloi, B.
    Dan, Pranab K.
    PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART B-JOURNAL OF ENGINEERING MANUFACTURE, 2017, 231 (03) : 505 - 522
  • [24] Prediction-based power-performance adaptation of multithreaded scientific codes
    Curtis-Maury, Matthew
    Blagojevic, Filip
    Antonopoulos, Christos D.
    Nikolopoulos, Dimitrios S.
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2008, 19 (10) : 1396 - 1410
  • [25] Watt matters most? Design space exploration of high-performance microprocessors for power-performance efficiency
    Trancoso, Pedro
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2007, 16 (03) : 357 - 378
  • [26] Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency
    Song, William J.
    Buyuktosunoglu, Alper
    Cher, Chen-Yong
    Bose, Pradip
    ISLPED '16: PROCEEDINGS OF THE 2016 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2016, : 284 - 289
  • [27] Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime
    Khan, O.
    Kundu, S.
    IET CIRCUITS DEVICES & SYSTEMS, 2012, 6 (05) : 355 - 365
  • [28] Optimum Power-Performance GPU Configuration Prediction based on Code Attributes
    Jooya, Ali
    Dimopoulos, Nikitas
    Baniasadi, Amirali
    2017 INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING & SIMULATION (HPCS), 2017, : 418 - 425
  • [29] Decreasing Use of High-Cost Imaging: The Danger of Utilization-Based Performance Measures
    Raja, All S.
    Walls, Ron M.
    Schuur, Jeremiah D.
    ANNALS OF EMERGENCY MEDICINE, 2010, 56 (06) : 597 - 599
  • [30] Optimising Power-Performance in SOI-based Null Convention Logic
    Le Huy, Nguyen
    Beckett, Paul
    2022 INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT), 2022, : 32 - 35