An activity monitor for power/performance tuning of CMOS digital circuits

被引：0
|
作者：
Rius, J
Pineda, J
Meijer, M
机构：
[1] Univ Politecn Cataluna, Dept Elect Engn, E-08028 Barcelona, Spain
[2] Philips Res Labs, Digital Design & Test Grp, NL-5656 AA Eindhoven, Netherlands
来源：
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2005年 / 3728卷
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The requirement to control each possible degree of freedom of digital circuits becomes a necessity in deep submicron technologies. This requires getting a set of monitors to measure each one of the parameters of interest. This paper describes a monitor fabricated in a 90nm CMOS technology which is able to estimate the circuit activity. The output of such monitor can be used as a tool to decide how to adjust the circuit working conditions to get the best power/performance circuit response. The paper presents the implementation and experimental results of a test chip including such monitor.
引用
收藏
页码：187 / 196
页数：10
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