Power and area efficient column-parallel ADC architectures for CMOS image sensors

被引：7

作者：

Snoeij, Martijn F. ^{[1
]}

Theuwissen, Albert J. P. ^{[1
,2
]}

Huijsing, Johan H. ^{[1
]}

Makinwa, Kofi A. A. ^{[1
]}

机构：

[1] Delft Univ Technol, Elect Instrumentat Lab DIMES, NL-2600 AA Delft, Netherlands

[2] DALSA Semicond, Eindhoven, Netherlands

来源：

2007 IEEE SENSORS, VOLS 1-3 | 2007年

关键词：

D O I：

10.1109/ICSENS.2007.4388451

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The ever-increasing resolution of CMOS imagers has had a profound impact on their analog readout electronics, and, in particular, on their ADC architecture. This paper gives an overview of the development of column-parallel ADCs that enable the high-speed and power-efficient readout of high-resolution CMOS imagers. In particular, the recently proposed multiple-ramp single-slope (MRSS) ADC will be discussed.

引用

页码：523 / 526

页数：4

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