Dynamically reconfigurable processor for multimedia application

被引：0
|
作者：
Mlinaric, H [1 ]
Duracic, K [1 ]
Kovac, M [1 ]
机构：
[1] Univ Zagreb, Fac Elect Engn & Comp, Dept Control & Comp Engn Automat, Comp Syst & Proc Grp, Zagreb 41000, Croatia
来源：
IWSSIP 2005: Proceedings of the 12th International Worshop on Systems, Signals & Image Processing | 2005年
关键词：
reconfigurable computing; FPGA; multimedia; MPEG;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents a dynamically reconfigurable processor designed for processing data in multimedia application. The work was done as resource of PhD. research and years of experience in processor architecture and multimedia audio and video application design. The object of this research is to build a high performance reconfigurable processor providing highly scalable architecture and transparent hardware reconfigurable for the multimedia application such as, video encoding/decoding, audio encoding/decoding, speech encoding/decoding.
引用
收藏
页码：141 / 144
页数：4
相关论文
共 50 条
  • [21] Dynamically Reconfigurable Register File for a Softcore VLIW Processor
    Wong, Stephan
    Anjam, Fakhar
    Nadeem, Faisal
    2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010), 2010, : 969 - 972
  • [22] A preemption algorithm for a multitasking environment on dynamically reconfigurable processor
    Tuan, Vu Manh
    Amano, Hideharu
    RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, 2008, 4943 : 172 - 184
  • [23] Implementation of a baseline RISC for the realization of a dynamically reconfigurable processor
    Najjar, Hajer
    Bourguiba, Riad
    Mounie, Jaouhar
    2015 IEEE 12TH INTERNATIONAL MULTI-CONFERENCE ON SYSTEMS, SIGNALS & DEVICES (SSD), 2015,
  • [24] DReAC: A novel dynamically reconfigurable co-processor
    Song, Yu-Kun
    Gao, Ming-Lun
    Deng, Hong-Hui
    Wang, Rui
    Hu, Yong-Hua
    Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2007, 35 (05): : 833 - 837
  • [25] A processor for genetic algorithm using dynamically reconfigurable memory
    Kanasugi, Akinori
    Tsukahara, Akihiko
    2006 INTERNATIONAL CONFERENCE ON HYBRID INFORMATION TECHNOLOGY, VOL 1, PROCEEDINGS, 2006, : 310 - +
  • [26] Implementing and evaluating stream applications on the dynamically reconfigurable processor
    Suzuki, N
    Kurotaki, S
    Suzuki, M
    Kaneko, N
    Anjo, K
    Motomura, M
    Wakabayashi, K
    Toi, T
    Awashima, T
    12TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2004, : 328 - 329
  • [27] POWER REDUCTION TECHNIQUES FOR DYNAMICALLY RECONFIGURABLE PROCESSOR ARRAYS
    Nishimura, T.
    Hirai, K.
    Saito, Y.
    Nakamura, T.
    Hasegawa, Y.
    Tsutsusmi, S.
    Tunbunheng, V.
    Amano, H.
    2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2, 2008, : 305 - 310
  • [28] Implementation of dynamically reconfigurable processor DAPDNA-2
    Sato, T
    Watanabe, H
    Shiba, K
    2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papers, 2005, : 323 - 324
  • [29] An image recognition processor using dynamically reconfigurable ALU
    Miyamoto, N
    Kotani, K
    Maruo, K
    Ohmi, T
    PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2004, : 599 - 602
  • [30] An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor
    Hasegawa, Y
    Abe, S
    Matsutani, H
    Amano, H
    Anjo, K
    Awashima, T
    FPT 05: 2005 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS, 2005, : 163 - 170
12345