Reuse of VLSI layout topology by parametric BSG

被引：0

作者：

Wu, ZL ^{[1
]}

Sakanushi, K ^{[1
]}

Kajitani, Y ^{[1
]}

机构：

[1] Tokyo Inst Technol, Dept Commun & Integrated Syst, Meguro Ku, Tokyo 152, Japan

来源：

2000 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS: ELECTRONIC COMMUNICATION SYSTEMS | 2000年

关键词：

layout; floorplan; BSG; parametric BSG; reuse;

D O I：

10.1109/APCCAS.2000.913646

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In reuse of a layout design of VSLI, we first determine the information to abstract from a given design, and then prepare a data structure to store it. Since a further optimization is required in the new environment, the data structure is required in the new environment, the data structure must be flexible to accept a change of the data. In this paper, the floorplan of a given layout is focused. It is characterized by a topographical property, called the seg-based 4-direction. The parametric BSG (PBSG) is proposed as the data structure. An elegant procedure to map the seg-based 4-direction into PBSG of the minimum size is given. Merits of using PBSG in reuse are discussed.

引用

页码：817 / 820

页数：4

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