Recognition of floorplan by parametric BSG for reuse of layout design

被引：0

作者：

Sakanushi, K ^{[1
]}

Wu, ZL

Kajitani, Y

机构：

[1] Tokyo Inst Technol, Dept Commun & Integrated Syst, Tokyo 1528552, Japan

[2] Kitakyushu Univ, Fac Int Environm Engn, Promot & Dev Off, Kitakyushu, Fukuoka 8028577, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2002年 / E85A卷 / 04期

关键词：

parametric BSG; layout; reuse; floorplan; technology migration;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In reuse of the VLSI layout design when technology migration takes place, the information to be abstracted from the original design and the data structure to store the information shall be specified, In this paper, they are assumed as the seg-based 4-direction and the parametric BSG, respectively. The parametric BSG is a BSG whose segs are generalized to take any number of units of length. The seg-based 4-direction is the right-of. left-of. above, and below relations between two rooms in accordance with the segs between them. An elegant procedure is given to map the floorplan of the model into a parametric BSG of the minimum size, keeping the abstracted seg-based 4-direction. Merits of the PBSC are discussed and a way of reuse is suggested by illustrative instances. Finally. a superior potential of the parametric BSG as the data structure is discussed empirically.

引用

页码：872 / 879

页数：8

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