The channeled-BSG: A universal floorplan for simultaneous place/route with IC applications

被引：12

作者：

Nakatake, S ^{[1
]}

Sakanushi, K ^{[1
]}

Kajitani, Y ^{[1
]}

Kawakita, M ^{[1
]}

机构：

[1] Tokyo Inst Technol, Dept Elect & Elect Engn, Tokyo 152, Japan

来源：

1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS | 1998年

关键词：

D O I：

10.1109/ICCAD.1998.742907

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The BSG-based packing of rectangles has been shown a breakthrough in problem size and generality, if routing is not involved. In order to include the routing, we define the channeled-BSG by associating the BSG-segs with channels. On the channeled-BSG, a new operation, flip, transforms an initial routing to another. Together with a formula that estimates the worst case width of channels for a given global routing, a solution space of simultaneous placement and routing is realized. It is proved that the space contains an optimal solution within the framework of the model. To search the space for a better solution, a simulated annealing is implemented. Experiments to industrial data of analog LSI's showed a promising performance.

引用

页码：418 / 425

页数：8