An efficient hardware interleaver for 3G turbo decoding

We describe an energy-efficient approach for VLSI implementation of the 3(rd) Generation Partnership Project (3GPP) turbo coding interleaver algorithm. Unlike previous implementations, this interleaver uses a two-stage dedicated hardware datapath that exploits the iterative nature of the decoding process, to compute addresses on the fly, eliminating the overhead associated with programmable processors and precomputed address storage. By separating the interleaving process into two stages, our architecture allows the preparatory phase to be turned off during iterations, while the decoder engages only the real-time address computation phase, further reducing power consumption.