Very low-complexity hardware interleaver for turbo decoding

被引：16
|
作者：
Wang, Zhongfeng [1 ]
Li, Qingwei
机构：
[1] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA
[2] Morph Technol Inc, Campbell, CA 95008 USA
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2007年 / 54卷 / 07期
关键词：
CDMA; interleaver; turbo codes; VLSI architecture;
D O I：
10.1109/TCSII.2007.895313
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This brief presents a very low complexity hardware interleaver implementation for turbo code in wideband CDMA (W-CDMA) systems. Algorithmic transformations are extensively exploited to reduce the computation complexity and latency. Novel VLSI architectures are developed. The hardware implementation results show that an entire turbo interleave pattern generation unit consumes only 4 k gates, which is an order of magnitude smaller than conventional designs.
引用
收藏
页码：636 / 640
页数：5
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