Optimization Design of 2.5D TSV Package Using Thermo-electrical Co-simulation Method

In this paper, a 2.5D TSV (through silicon via) package is designed for handheld device. A high performance Application Processor die and a Memory die with the sizes of 7.535x7.616x0.15 mm(3) and 7.336x3.604x0.15 mm(3), respectively, are integrated on a silicon interposer with a large number of TSVs. The backside and front of the interposer have one and two layers of redistribution layer (RDL), respectively. Each layer of RDL is about 3 similar to 5 mu m and the minimum line width / pitch of the RDL in the interposer are 10 mu m /10 mu m. In order to investigate the thermal performance of the package, IR drop of Power and Ground (P/G) Nets of the Processor and Memory dies, and the mutual effects of them, the paper conducts the following researches: First of all, only thermal simulation is done to investigate the thermal performance of the 2.5D TSV package using Cadence Sigrity PowerDC. The highest junction temperatures of Processor and Memory dies are evaluated. When the ambient temperature is 25 degrees C, the junction temperatures of Processor and Memory dies are 62.7 degrees C and 56 degrees C, respectively, which are relatively higher for handheld device. Then, thermal and optimization designs are conducted to improve the thermal performance of the 2.5D TSV package. An aluminum heat spreader is employed, attached to the top surface of the 2.5D TSV package through high heat conductive thermal interface material (TIM). The effects of heat spreader size on the highest junction temperatures of Processor and Memory dies are studied and a heat spreader size of 60x60x2 mm(3) is chosen. Thirdly, thermal simulation and thermoelectrical co-simulation are compared to study the effects of P/G Nets of the both dies on the thermal performance of the 2.5D TSV package. It is found that P/G Nets could increase the junction temperature of the both dies. Fourthly, IR drop analysis and thermo-electrical co-simulation are compared to study the effects of the heat dissipation issues of the package on the IR drop of P/G Nets of the both dies. The study shows that the heat could increase the IR drop of P/G Nets of the both dies and IR drop of VDDCPU of the Processor die is the biggest. Fifthly, aiming at the VDDCPU of Processor die, optimization design is carried out to reduce the IR drop of VDDCPU. After optimization, IR drop of VDDCPU decreases by 45.3%. IR drop decreases to an acceptable value. Therefore, P/G Nets of the dies should be considered when conducting thermal simulation of the package, and heat dissipation issues of the package should also be considered when analyzing IR drop of P/G Nets of the dies.