CMOS Programmable Divider for Zigbee Frequency Synthesizer

被引：0

作者：

Ismail, Nesreen M. H. ^{[1
]}

Othman, Masuri ^{[1
]}

机构：

[1] Univ Kebangsaan Malaysia, Inst MicroEngn & NanoElect, Bangi 43600, Malaysia

来源：

2009 3RD INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS (SCS 2009) | 2009年

关键词：

Integer N Divider; Phase Locked Loop; Programmable Divider; Zigbee;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents 4-bit integer N CMOS programmable frequency divider with high speed and low power consumption. It is based on a 15/16 dual-modulus prescaler, and programmable asynchronous and synchronous dividers. It works up to 3.4 GHz frequency clock and consumes 0.7 mW. It is tested in PLL for 2.4GHz band Zigbee standard. All results are taken from simulating extracted layout. It is implemented using Silterra 0.18-mu m CMOS process, and voltage supply 1.8V.

引用

页码：420 / 422

页数：3

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