All-digital successive approximation TDC in time-mode signal processing

The need for low-power high-resolution ADCs in a broad range of emerging applications and the architecture to realize these ADCs are examined. The pros and cons of various TDC architectures namely flash TDC, Vernier TDC, Delta Sigma TDC, and SAR TDC are compared and their suitability for implementing hybrid ADCs to achieve low power and high resolution is investigated. An 8-bit time-mode SAR TDC targeting hybrid ADCs is proposed. The proposed SAR TDC uses a pair of 16-stage pre-skewed delay lines with 16-level digital time interpolation to achieve the targeted resolution and desired power efficiency. The impact of the degree of pre-skewing on both resolution and power consumption is investigated. The nonlinearity of the pre-skewed delay lines is also investigated, along with the impact of PVT uncertainty. The nonlinearity of the digital time interpolators and the impact of PVT uncertainty on time interpolators are also studied. Factors affecting the linearity of digital time interpolators including input-output isolation and input slope are investigated. A detailed treatment of the timing errors arising from device noise and mismatch is provided. The SAR TDC is designed in a TSMC 65 nm 1.0 V CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results show the SAR TDC operated at 10 MS/s achieves 0.33 ps resolution, 84.8 ps measurement range, 7-bits ENOB, and 1.30 pJ/conversion power efficiency.