Convective heat transfer from a die-stacked electronic package

被引:4
|
作者
Natarajan, Venkat [1 ]
机构
[1] Intel Technol India Pvt Ltd, Bangalore 560001, Karnataka, India
关键词
D O I
10.1109/ITHERM.2008.4544388
中图分类号
O414.1 [热力学];
学科分类号
摘要
Convective heat transfer from a vertically stacked [3-D] electronic package (die-stacking) mounted in between two circuit boards is numerically investigated. Heat transfer characteristics of single chip packages and multiple-die packages for both two and four die stack are presented and compared. The package Reynolds number, based on the package height and upstream velocity, ranges from 150 to about 1000. The channel aspect ratios is approximately H/B = 9 with flow bypass > 5B, wherein B is package height and W is the height of the channel. The effect of board conduction on the heat transfer performance from the package is also quantified. A valuable finding is that, in the present set of configurations, the heat transfer for a multi-die stack, such as a two-die stack or a four-die stack, can be reasonably predicted using the heat transfer information from a single chip package by employing a simple scalar factor. Finally, the effects of non-uniform heating on the die temperatures of the different packages in a stack are examined.
引用
收藏
页码:1132 / 1138
页数:7
相关论文
共 50 条
  • [1] Convective heat transfer from a stacked electronic package
    Natarajan, Venkat
    2007 International Conference on Thermal Issues in EmergingTechnologies - Theory and Applications, 2007, : 112 - 118
  • [2] Convective heat transfer distribution on the surface of an electronic package
    Wirtz, R.A.
    Mathur, Ashok
    Journal of Electronic Packaging, Transactions of the ASME, 1994, 116 (01): : 49 - 54
  • [3] Efficient RAS Support for Die-stacked DRAM
    Jeon, Hyeran
    Loh, Gabriel H.
    Annavaram, Murali
    2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2014,
  • [4] Power Profiling of Modern Die-Stacked Memory
    Stow, Dylan
    Farmahini-Farahani, Amin
    Gurumurthi, Sudhanva
    Ignatowski, Michael
    Xie, Yuan
    IEEE COMPUTER ARCHITECTURE LETTERS, 2019, 18 (02) : 132 - 135
  • [5] A Software-managed Approach to Die-stacked DRAM
    Oskin, Mark
    Loh, Gabriel H.
    2015 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURE AND COMPILATION (PACT), 2015, : 188 - 200
  • [6] Heterogeneous Memory Architectures: A HW/SW Approach for Mixing Die-stacked and Off-package Memories
    Meswani, Mitesh R.
    Blagodurov, Sergey
    Roberts, David
    Slice, John
    Ignatowski, Mike
    Loh, Gabriel H.
    2015 IEEE 21ST INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2015, : 126 - 136
  • [7] A CONFIGURABLE AND STRONG RAS SOLUTION FOR DIE-STACKED DRAM CACHES
    Sim, Jaewoong
    Loh, Gabriel H.
    Sridharan, Vilas
    O'Connor, Mike
    IEEE MICRO, 2014, 34 (03) : 80 - 90
  • [8] Deploying Hash Tables on Die-Stacked High Bandwidth Memory
    Cheng, Xuntao
    He, Bingsheng
    Lo, Eric
    Wang, Wei
    Lu, Shengliang
    Chen, Xinyu
    PROCEEDINGS OF THE 28TH ACM INTERNATIONAL CONFERENCE ON INFORMATION & KNOWLEDGE MANAGEMENT (CIKM '19), 2019, : 239 - 248
  • [9] Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
    Jevdjic, Djordje
    Loh, Gabriel H.
    Kaynak, Cansu
    Falsafi, Babak
    2014 47TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), 2014, : 25 - 37
  • [10] NOVEL 3D DIE-STACKED OPTO-ELECTRONIC TRANSCEIVER ICs THAT ALLOW FOR WAFERSCALE FABRICATION
    Duan, Pinxiang
    Raz, Oded
    Dorren, Harmen J. S.
    2013 18TH MICROOPTICS CONFERENCE (MOC), 2013,