Implementation of a CMOS mixed-signal digital FLC chip using new Fuzzifier and current mode A/D

被引：0
|
作者：
Yosefi, Gh. [1 ]
Aminifar, S. [1 ]
机构：
[1] Islamic Azad Univ Mahabad, Mahabad 59135, Iran
来源：
2007 6TH INTERNATIONAL CONFERENCE ON INFORMATION, COMMUNICATIONS & SIGNAL PROCESSING, VOLS 1-4 | 2007年
关键词：
CMOS; FLC chip; fuzzification; min operator; A/D converter; current mode circuits;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper we design a new Fuzzy Logic controller (FLC) chip with mixed-signal input and digital output. For implementing this idea, a new programmable Fuzzifier circuit based on generation of three current membership functions including Gaussian, Trapezoidal and Triangular shapes and three new circuits for implementing Min operators are proposed. We improved a Multiplier/Divider circuit and a current mode Analog to Digital (AID) converter with 7bit resolutions to complete and implement Defuzzifier block. The proposed controller was designed less than 0.1 mm(2) in 0.35um CMOS standard technology. The inference speed and Power consumption of the controller are about 16.6 MFLIPS and 13.4mw respectively.
引用
收藏
页码：996 / 1000
页数：5
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