Implementation of a CMOS mixed-signal digital FLC chip using new Fuzzifier and current mode A/D

In this paper we design a new Fuzzy Logic controller (FLC) chip with mixed-signal input and digital output. For implementing this idea, a new programmable Fuzzifier circuit based on generation of three current membership functions including Gaussian, Trapezoidal and Triangular shapes and three new circuits for implementing Min operators are proposed. We improved a Multiplier/Divider circuit and a current mode Analog to Digital (AID) converter with 7bit resolutions to complete and implement Defuzzifier block. The proposed controller was designed less than 0.1 mm(2) in 0.35um CMOS standard technology. The inference speed and Power consumption of the controller are about 16.6 MFLIPS and 13.4mw respectively.