AN AVS/H.264 DUAL MODE VIDEO DECODER TARGETED AT HIGH DEFINITION VIDEO APPLICATIONS

被引：0

作者：

Chien, Cheng-An ^{[1
]}

Yang, Yao-Chang ^{[1
]}

Yang, Feng-Ming ^{[1
]}

Chen, Jia-Wai ^{[1
]}

Chang, Hsiu-Cheng ^{[1
]}

Guo, Jiun-In ^{[1
]}

机构：

[1] Natl Chung Cheng Univ, Chiayi, Taiwan

来源：

2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | 2011年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes an AVS/H.264 dual mode video decoder targeted at high definition video applications. The proposed design is compatible to decode H.264-BP/MP/HP and AVS-JP bit-streams with optimization on both system and component levels. On system level, we simplify the control of H. 264 MBAFF coding, and reduce buffer size for storing prediction data. On component level, we improve the throughput in bit-stream decoding and integrate AVS/H.264 processing units together to reduce hardware cost. Through the optimization techniques, the proposed design can achieve real-time HD1080 (1920x1088@30Hz) decoding at 150MHz.

引用

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页码：285 / 288

页数：4

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