Fabrication and performance of integrated capacitors on silicon and flexible substrates

The High Density Electronics Center (HiDEC) at the University of Arkansas has developed a method for fabricating integrated thin film tantalum oxide capacitors on silicon and flexible substrates. These capacitors may be located close to the chip by incorporating them into MCM substrates themselves attaching them to the surface of the package, or by bonding them to substrate pads underneath the die. The capacitors consist of sputtered copper bottom plates, anodized Ta dielectric and sputtered Cu top plates. Both floating plate and parallel plate designs were developed The parallel plate capacitors are generally simpler to fabricate since they require one fewer mask and etch step than parallel plate configurations. Several test structures were developed and were used to measure capacitance, resistance, inductance, and breakdown voltage. Capacitance values ranged from 50-180 nF/cm(2) and exhibited low impedance into the range of several GHz. Leakage values were below 10(-6) A/cm(2) at IO volts and effective series resistances were less than 10 milliohms. Defect densities studies were also performed to show the advantages of anodization over sputtering. Thermal annealing effects were also investigated to determine the feasibility of incorporating these structures into high-power single chip and multi-chip packaging.