Design optimization for capacitive-resistively driven on-chip global interconnect

被引：3
|
作者：
Jiang, Jianfei [1 ]
He, Weifeng [1 ]
Wei, Jizeng [2 ]
Wang, Qin [1 ]
Mao, Zhigang [1 ]
机构：
[1] Shanghai Jiao Tong Univ, Shanghai 200240, Peoples R China
[2] Tianjin Univ, Tianjin 300072, Peoples R China
来源：
IEICE ELECTRONICS EXPRESS | 2015年 / 12卷 / 08期
基金：
国家高技术研究发展计划(863计划); 中国国家自然科学基金;
关键词：
AC coupling; global interconnect; high speed; on-chip; low power; COMMUNICATION; TRANSCEIVER; SPEED; WIRES; CMOS;
D O I：
10.1587/elex.12.20150111
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
On-chip global wires are speed and power bottleneck in state-of-the-art chips. AC coupling technique is an efficient way to reduce interconnection delay and power. This paper proposes a new capacitive-resistively driven AC coupling global link. Bandwidth performance of the proposed wire is analyzed and an optimization algorithm for capacitive-resistively driven wire is presented. Simulation results show that our optimization methodology can improve the bandwidth. By applying our optimization algorithm, data rate can be improved from 2 Gb/s to 2.5 Gb/s in the implemented transceiver circuit. The proposed optimization algorithm can be applied in high speed global communication.
引用
收藏
页码：1 / 12
页数：12
相关论文
共 50 条
  • [41] Alternate self-shielding for high-speed and reliable on-chip global interconnect
    Yuyama, Y
    Tsuchiya, A
    Kobayashi, K
    Onodera, H
    IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (03): : 327 - 333
  • [42] Faster Delay modeling and Power optimization for On-Chip Global Interconnects
    Aswatha, A. R.
    Basavaraju, T.
    ICSE: 2008 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2008, : 82 - 86
  • [43] Global interconnect design in a three-dimensional system-on-a-chip
    Joyner, JW
    Zarkesh-Ha, P
    Meindl, JD
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (04) : 367 - 372
  • [44] Power-driven design of router microarchitectures in on-chip networks
    Wang, H
    Peh, LS
    Malik, S
    36TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, 2003, : 105 - 116
  • [45] Design and measurement of an inductance-oscillator for analyzing inductance impact on on-chip interconnect delay
    Sato, T
    Masuda, H
    4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2003, : 395 - 400
  • [46] Design High Bandwidth-Density, Low Latency and Energy Efficient On-Chip Interconnect
    Wang, Yong
    Wu, Hui
    2017 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2017,
  • [47] Topology optimization of on-chip integrated laser-driven particle accelerator
    He, Yang-Fan
    Sun, Bin
    Ma, Ming-Jiang
    Li, Wei
    He, Qiang-You
    Cui, Zhi-Hao
    Wang, Shao-Yi
    Zhao, Zong-Qing
    NUCLEAR SCIENCE AND TECHNIQUES, 2022, 33 (09)
  • [48] Topology optimization of on-chip integrated laser-driven particle accelerator
    Yang-Fan He
    Bin Sun
    Ming-Jiang Ma
    Wei Li
    Qiang-You He
    Zhi-Hao Cui
    Shao-Yi Wang
    Zong-Qing Zhao
    Nuclear Science and Techniques, 2022, 33
  • [49] Topology optimization of on-chip integrated laser-driven particle accelerator
    Yang-Fan He
    Bin Sun
    Ming-Jiang Ma
    Wei Li
    Qiang-You He
    Zhi-Hao Cui
    Shao-Yi Wang
    Zong-Qing Zhao
    Nuclear Science and Techniques, 2022, 33 (09) : 128 - 138
  • [50] DESIGN AND OPTIMIZATION OF ON-CHIP VOLTAGE REGULATORS FOR HIGH PERFORMANCE APPLICATIONS
    Zhou, Pingqiang
    2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
12345