Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes

被引：10
|
作者：
Dey, S. [1 ]
Jena, J. [1 ]
Mohapatra, E. [1 ]
Dash, T. P. [1 ]
Das, S. [2 ]
Maiti, C. K. [1 ]
机构：
[1] Siksha O Anusandhan Deemed Be Univ, Dept Elect & Commun Engn, Bhubaneswar 75030, Odisha, India
[2] Silicon Inst Technol, Dept Elect & Commun Engn, Bhubaneswar 75104, Odisha, India
来源：
PHYSICA SCRIPTA | 2020年 / 95卷 / 01期
关键词：
vertically-stacked nanowire FETs; quantum confinement; technology computer aided design (TCAD); density-gradient (DG) model; metal grain granularity (MGG);
D O I：
10.1088/1402-4896/ab4621
中图分类号：
O4 [物理学];
学科分类号：
0702 ;
摘要：
Gate-all-around (GAA) cylindrical Si channel nanowire field-effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3D TCAD physics-based simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3 nm using quantum corrected 3D density gradient finite element simulations. Simulations are also performed to study the effects of process-induced variabilities, such as metal grain granularity (MGG) on 3 nm gate length device performance in the sub-threshold region. The importance of MGG induced variability for gate-all-around stacked devices having 3 horizontal nanowires in the 3 nm technology nodes is shown.
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收藏
页数：9
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