Design of Error-Compensated Fixed-Width Multiplier

被引：0
|
作者：
Junghare, Aniket V. [1 ]
Keote, Rashmi S. [1 ]
Karule, P. T. [1 ]
机构：
[1] Yeshwantrao Chavan Coll Engn, Dept Elect Engn, Nagpur, Maharashtra, India
来源：
2015 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP) | 2015年
关键词：
Compensation Circuit; Error Compensation; Fixed Width Multiplier; Low error; DSP APPLICATIONS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents an error compensation method for fixed-width multipliers. The analysis for the truncation part is done and accordingly the compensation circuit is made. Here design of 6-bit fixed-width multiplier is done using Xilinx. The simulation results show significant improvement in terms of delay and also save area.
引用
收藏
页码：1675 / 1678
页数：4
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