A low-error and area-time efficient fixed-width booth multiplier

In this paper, we develop a new methodology for designing a lower-error and area-time efficient 2 s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index and binary thresholding, we derive a better error-compensation bias to reduce the truncation error. Since the proposed error-compensation bias is realizable, the constructing low-error fixed-width Booth multiplier is area-time efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multiplier to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier.