Design of Error-Compensated Fixed-Width Multiplier

被引：0
|
作者：
Junghare, Aniket V. [1 ]
Keote, Rashmi S. [1 ]
Karule, P. T. [1 ]
机构：
[1] Yeshwantrao Chavan Coll Engn, Dept Elect Engn, Nagpur, Maharashtra, India
来源：
2015 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP) | 2015年
关键词：
Compensation Circuit; Error Compensation; Fixed Width Multiplier; Low error; DSP APPLICATIONS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents an error compensation method for fixed-width multipliers. The analysis for the truncation part is done and accordingly the compensation circuit is made. Here design of 6-bit fixed-width multiplier is done using Xilinx. The simulation results show significant improvement in terms of delay and also save area.
引用
下载
收藏
页码：1675 / 1678
页数：4
相关论文
共 50 条
  • [1] Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series
    Wen-Quan He
    Yuan-Ho Chen
    Shyh-Jye Jou
    Circuits, Systems, and Signal Processing, 2016, 35 : 2972 - 2991
  • [2] Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series
    He, Wen-Quan
    Chen, Yuan-Ho
    Jou, Shyh-Jye
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2016, 35 (08) : 2972 - 2991
  • [3] Design of low error CSD fixed-width multiplier
    Kim, SM
    Chung, JG
    Parhi, KK
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, PROCEEDINGS, 2002, : 69 - 72
  • [4] Design of the lower error fixed-width multiplier and its application
    Van, LD
    Wang, SS
    Feng, WS
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2000, 47 (10) : 1112 - 1118
  • [5] Design of low-error fixed-width modified booth multiplier
    Cho, KJ
    Lee, KC
    Chung, JG
    Parhi, KK
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (05) : 522 - 531
  • [6] Design of low-error fixed-width multiplier for DSP applications
    Jou, JM
    Kuang, SR
    ELECTRONICS LETTERS, 1997, 33 (19) : 1597 - 1598
  • [7] Low error fixed-width modified booth multiplier
    Cho, KJ
    Lee, KC
    Chung, JG
    Parhi, KK
    2002 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, 2002, : 45 - 50
  • [8] Fixed-Width Group CSD Multiplier Design
    Kim, Yong-Eun
    Cho, Kyung-Ju
    Chung, Jin-Gyun
    Huang, Xinming
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, E93D (06): : 1497 - 1503
  • [9] Error Compensation Techniques for Fixed-Width Array Multiplier Design - A Technical Survey
    Balamurugan, S.
    Mallick, P. S.
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2017, 26 (03)
  • [10] Design of a lower-error fixed-width multiplier for speech processing application
    Van, Lan-Da
    Wang, Shuenn-Shyang
    Tenqchen, Shing
    Feng, Wu-Shiung
    Jeng, Bor-Shenn
    Proceedings - IEEE International Symposium on Circuits and Systems, 1999, 3
12345