Low-Phase-Noise Wide-Frequency-Range Ring-VCO-Based Scalable PLL with Subharmonic Injection Locking in 0.18 μm CMOS

A low-phase-noise ring-VCO-based PLL (frequency tuning range: 0.65-1.6 GHz) with subharmonic injection locking was realized (PLL area: 0.1 mm(2)) by adopting 0.18 mu m CMOS technology and combining pMOS resistive loads with a circuit for shifting bias levels; this makes the rail-to-rail range of voltages usable as control voltages. For a 90-MHz input reference signal, without injection locking, the 0.2-MHz-offset phase noise was -108 dBc/Hz (PLL output frequency: 1.44GHz = 16 x 90MHz); with injection locking, the noise was -122 dBclHz (spurious level: -35 dBc; power consumption from a 1.8V power supply: 39mW).