Temporary bonding for Chips In Wafer Processing

被引:0
|
作者
Souriau, Jean-Charles [1 ]
Jouve, Amandine [2 ]
Sillon, Nicolas [1 ]
机构
[1] CEA LETI Minatec, 17 Rue Martyrs, F-38054 Grenoble 9, France
[2] Brewer Sci Inc, Rolla, MO 65401 USA
关键词
D O I
10.1109/EPTC.2009.5416513
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Chip In Wafer is a very challenging concept because this solution allows wafer scale processes for System in Package and a very high miniaturization and performance level. This paper describes a technologies developed for Chip integration In Wafer (CIW). The approach consists in reconstituting a wafer from heterogeneous chips embedded in a resin with the active sides coplanar. This paper present the development of a new process using wafer substrate including alignment marks and a transparence adhesive which allow an accurate dies positioning and holding during the polymer molding. The process presented in this paper is compatible for chips in polymer wafer, chips in silicon wafer, chips in glass wafer and some other frame.
引用
收藏
页码:412 / +
页数:2
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