Temporary bonding for Chips In Wafer Processing

被引:0
|
作者
Souriau, Jean-Charles [1 ]
Jouve, Amandine [2 ]
Sillon, Nicolas [1 ]
机构
[1] CEA LETI Minatec, 17 Rue Martyrs, F-38054 Grenoble 9, France
[2] Brewer Sci Inc, Rolla, MO 65401 USA
关键词
D O I
10.1109/EPTC.2009.5416513
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Chip In Wafer is a very challenging concept because this solution allows wafer scale processes for System in Package and a very high miniaturization and performance level. This paper describes a technologies developed for Chip integration In Wafer (CIW). The approach consists in reconstituting a wafer from heterogeneous chips embedded in a resin with the active sides coplanar. This paper present the development of a new process using wafer substrate including alignment marks and a transparence adhesive which allow an accurate dies positioning and holding during the polymer molding. The process presented in this paper is compatible for chips in polymer wafer, chips in silicon wafer, chips in glass wafer and some other frame.
引用
收藏
页码:412 / +
页数:2
相关论文
共 50 条
  • [31] The effect of temporary bonding on post processing in TSV interposer manufacturing
    Wang, Qibing
    Yu, Daquan
    Jiang, Feng
    Liu, Haiyan
    Jing, Xiangmeng
    [J]. MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2015, 21 (04): : 749 - 755
  • [32] The effect of temporary bonding on post processing in TSV interposer manufacturing
    Qibing Wang
    Daquan Yu
    Feng Jiang
    Haiyan Liu
    Xiangmeng Jing
    [J]. Microsystem Technologies, 2015, 21 : 749 - 755
  • [33] Optimization of Temporary Wafer Bonding Materials and Processes for 3D IC Integration
    Ou-Yang, T. Y.
    Chang, H. H.
    Hsu, C. K.
    [J]. 2020 15TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT 2020), 2020, : 36 - 39
  • [34] Collective fabrication of all-organic microcantilever chips based on a hierarchical combination of shadow-masking and wafer-bonding processing methods
    Dubourg, Georges
    Fadel-Taris, Ludivine
    Dufour, Isabelle
    Pellet, Claude
    Ayela, Cedric
    [J]. JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2011, 21 (09)
  • [35] A Review of Wafer Bonding Materials and Characterizations to enable Wafer Thinning, Backside Processing, and Laser Dicing
    Williams, G.
    O'Hara, P.
    Moore, J.
    Gordon, B.
    Rose, J.
    [J]. 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, : 164 - 164
  • [36] Temporary Bonding Material Study for Room Temperature Mechanical Debonding with eWLB Wafer Application
    Masuda, Seiya
    Iwai, Yu
    Sawano, Mitsuru
    Okabe, Kotaro
    Shimada, Kazuto
    Caparas, Jose Alvin
    Choi, Won Kyoung
    [J]. 2018 IEEE 20TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2018, : 500 - 503
  • [37] Life cycle assessment of silicon wafer processing for microelectronic chips and solar cells
    Mario Schmidt
    Heidi Hottenroth
    Martin Schottler
    Gabriele Fetzer
    Birgit Schlüter
    [J]. The International Journal of Life Cycle Assessment, 2012, 17 : 126 - 144
  • [38] Life cycle assessment of silicon wafer processing for microelectronic chips and solar cells
    Schmidt, Mario
    Hottenroth, Heidi
    Schottler, Martin
    Fetzer, Gabriele
    Schlueter, Birgit
    [J]. INTERNATIONAL JOURNAL OF LIFE CYCLE ASSESSMENT, 2012, 17 (02): : 126 - 144
  • [39] Temporary Wafer Carrier for Thin Wafer Handling
    Masteika, V.
    Rogers, T.
    Santilli, R.
    [J]. 2017 5TH INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D), 2017, : 61 - 61
  • [40] Printable optically transparent adhesive processing for bonding of LED chips to packages
    Shih, Yu-Chou
    Kim, Gunwoo
    You, Jiun-Pyng
    Shi, Frank G.
    [J]. MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2016, 56 : 155 - 159