Schemes of clock recovery and synchronization in HDTV decoder SoC

被引：0
|
作者：
Zhang, CR [1 ]
Zheng, SB [1 ]
Wang, F [1 ]
Wang, T [1 ]
机构：
[1] Shanghai Jiao Tong Univ, Inst Image Commun & Informat Proc, Shanghai 200030, Peoples R China
来源：
Proceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology | 2005年
关键词：
D O I：
10.1109/IWVDVT.2005.1504613
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
In this paper, we present some design schemes of system clock recovery and synchronization in HDTV decoder SoC. First, a model of system clock recovery is introduced. Based on this model, an optimized hardware implementation is proposed. And then the scheme of synchronization about presentation and decoding is discussed. In the end, a solution to ensure decoding in abnormal conditions is explained.
引用
收藏
页码：312 / 315
页数：4
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