A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

被引：51

作者：

Balan, V ^{[1
]}

Caroselli, J

Chern, JG

Chow, C

Dadi, R

Desai, C

Fang, L

Hsu, D

Joshi, P

Kimura, H

Liu, CY

Pan, TW

Park, R

You, C

Zeng, Y

Zhang, E

Zhong, F

机构：

[1] LSI Log Corp, Commun & ASIC Technol Dept, Milpitas, CA 95035 USA

[2] LinkAMedia Inc, Santa Clara, CA 95051 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2005年 / 40卷 / 09期

关键词：

adaptive equalization; backplane transceiver; decision feedback equalization (DFE); SerDes; serial link;

D O I：

10.1109/JSSC.2005.848180

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40" of FR4 copper back-plane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13-mu m standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions.

引用

页码：1957 / 1967

页数：11

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