共 50 条
- [35] Design of Optimized Reversible Binary Adder/Subtractor and BCD Adder 2014 INTERNATIONAL CONFERENCE ON CONTEMPORARY COMPUTING AND INFORMATICS (IC3I), 2014, : 774 - 779
- [36] A novel reversible ternary coded decimal adder/subtractor Journal of Ambient Intelligence and Humanized Computing, 2021, 12 : 7745 - 7763
- [38] Towards quantum reversible ternary coded decimal adder Quantum Information Processing, 2017, 16
- [39] Novel High-Speed Architecture for 32-Bit Binary Coded Decimal (BCD) Multiplier 2008 INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES, 2008, : 542 - 545