A novel reversible ternary coded decimal adder/subtractor

被引:7
|
作者
Asadi, Mohammad-Ali [1 ]
Mosleh, Mohammad [1 ]
Haghparast, Majid [2 ]
机构
[1] Islamic Azad Univ, Dept Comp Engn, Dezful Branch, Dezful, Iran
[2] Islamic Azad Univ, Dept Comp Engn, Yadegar e Imam Khomeini RAH Shahre Rey Branch, Tehran, Iran
关键词
Quantum realization; Reversible circuit; Ternary coded decimal (TCD); Full-adder; Ternary coded decimal detector; PARALLEL ADDER/SUBTRACTOR; DESIGN;
D O I
10.1007/s12652-020-02499-6
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Reversible ternary logic is a promising new research for the future of quantum computing, which has several advantages over the binary ones. In this paper, an effective design of reversible ternary coded decimal (TCD) adder/subtractor is proposed. For this purpose, at first, we propose a new reversible ternary full-adder, called comprehensive reversible ternary full-adder, using the ternary logic capabilities that can sum four ternary values and produce two ternary outputs. Moreover, we implement a 3-qutrit ripple carry adder (RCA). Then, we propose a quantum realization of TCD error detector circuit. Next, a novel quantum reversible TCD adder and a novel quantum reversible TCD subtractor are designed and implemented using the proposed 3-qutrit RCA and the proposed TCD error detector. Finally, by merging these two circuits, we propose an effective quantum realization of reversible TCD adder/subtractor. The results of evaluations show that the proposed circuits are superior or similar to related counterpart works in terms of constant input, garbage outputs, hardware complexity and quantum cost criteria.
引用
收藏
页码:7745 / 7763
页数:19
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