Parallelizing and optimizing a simulator kernel on a multi-DSP architecture

被引:0
|
作者
Riel, A
Brenner, E
机构
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This paper describes our experiences with the parallelization and optimization of a hydraulic simulator kernel on a multi-DSP platform. Three different parallel versions of the initially sequential simulator have been implemented and optimized with respect to various hardware- and software-related issues. We discuss the paradigms applied for parallelization and the effects certain optimizations have on the simulator's performance. The focus of this research lies in providing measured comparable data of speedup and simulation times for all parallel versions of the same simulator in order to judge the relevance of different parallelization approaches and optimization efforts for a real-time implementation. Selected sets of these data are included and interpreted in this paper.
引用
收藏
页码:535 / 541
页数:7
相关论文
共 50 条
  • [21] The structure and application of a new multi-DSP parallel computing architecture based on ADSP-2106x
    Wang, ZB
    Tang, J
    Wang, XT
    Peng, YN
    [J]. 2001 CIE INTERNATIONAL CONFERENCE ON RADAR PROCEEDINGS, 2001, : 590 - 594
  • [22] An efficient and flexible modelling approach for multi-DSP system
    Zhou, Zheng-Mao
    Zhong, Shun-Hong
    Cai, Ming
    [J]. Computer Modelling and New Technologies, 2014, 18 (08): : 91 - 99
  • [23] Design of Multi-DSP Digital Signal Processing System
    Zhang Zhaohui
    [J]. PROCEEDINGS OF 2018 INTERNATIONAL CONFERENCE ON INFORMATION SYSTEMS AND COMPUTER AIDED EDUCATION (ICISCAE 2018), 2018, : 231 - 234
  • [24] eModularized reconfigurable system for target recognition with multi-DSP processing
    Li, Yun
    Li, Huili
    Xie, Xiaoming
    [J]. MIPPR 2013: REMOTE SENSING IMAGE PROCESSING, GEOGRAPHIC INFORMATION SYSTEMS, AND OTHER APPLICATIONS, 2013, 8921
  • [25] Design Pruning of DSP Kernel for Multi Objective IP Core Architecture
    Sengupta, Anirban
    [J]. 2019 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE), 2019,
  • [26] Multi-DSP hierarchical architecture with field-programmable logic for hard-field tomography sensors
    Castillo, Sergio Garcia
    Ozanyan, Krikor B.
    [J]. 2006 IEEE SENSORS, VOLS 1-3, 2006, : 650 - +
  • [27] Multi-DSP signal analyzer based on network instrument bus
    Song, Kaichen
    Zhu, Zhijuan
    Ye, Lingyun
    Luo, Xinfa
    [J]. PROCEEDINGS OF THE 2006 IEEE/ASME INTERNATIONAL CONFERENCE ON MECHATRONIC AND EMBEDDED SYSTEMS AND APPLICATIONS, 2006, : 403 - +
  • [28] Dynamic mixed signal processing instrument based on multi-DSP
    Wang, Y
    Lü, HB
    Su, SJ
    Ye, XB
    Tang, GL
    [J]. ISTM/99: 3RD INTERNATIONAL SYMPOSIUM ON TEST AND MEASUREMENT, 1999, : 237 - 241
  • [29] Parallel processing of H.264 on a multi-DSP platform
    Xi, Jie
    Chen, Jie
    Liu, Jian
    Ao, Tian-Yong
    [J]. Harbin Gongcheng Daxue Xuebao/Journal of Harbin Engineering University, 2010, 31 (06): : 736 - 742
  • [30] Rapid prototyping of flexible embedded systems on multi-DSP architectures
    Rinner, B
    Schmid, M
    Weiss, R
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, 2003, : 204 - 209