SANTA: Self-aligned nanotrench ablation via Joule heating for probing sub-20 nm devices

被引:3
|
作者
Xiong, Feng [1 ,3 ]
Deshmukh, Sanchit [1 ]
Hong, Sungduk [2 ]
Dai, Yuan [2 ]
Behnam, Ashkan [2 ]
Lian, Feifei [1 ]
Pop, Eric [1 ]
机构
[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA
[2] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA
[3] Univ Pittsburgh, Dept Elect & Comp Engn, Pittsburgh, PA 15261 USA
基金
美国国家科学基金会;
关键词
nanolithography; carbon nanotubes; graphene; finite element; self-aligned fabrication; nanoscale thermal transport; WALLED CARBON NANOTUBES; GRAPHENE TRANSISTORS; SILICON NANOWIRES; DEPOSITION; TRANSPORT; RIBBONS; NANOGAP; ARRAY;
D O I
10.1007/s12274-016-1180-0
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
Manipulating materials at the nanometer scale is challenging, particularly if alignment with nanoscale electrodes is desired. Here, we describe a lithography-free, self-aligned nanotrench ablation (SANTA) technique to create nanoscale "trenches" in a polymer like poly(methyl methacrylate) (PMMA). The nanotrenches are self-aligned with carbon nanotube (CNT) or graphene ribbon electrodes through a simple Joule heating process. Using simulations and experiments we investigated how the Joule power, ambient temperature, PMMA thickness, and substrate properties affect the spatial resolution of this technique. We achieved sub-20 nm nanotrenches, for the first time, by lowering the ambient temperature and reducing the PMMA thickness. We also demonstrated a functioning nanoscale resistive memory (RRAM) bit selfaligned with a CNT control device, achieved through the SANTA approach. This technique provides an elegant and inexpensive method to probe nanoscale devices using self-aligned electrodes, without the use of conventional alignment or lithography steps.
引用
收藏
页码:2950 / 2959
页数:10
相关论文
共 18 条
  • [1] SANTA: Self-aligned nanotrench ablation via Joule heating for probing sub-20 nm devices
    Feng Xiong
    Sanchit Deshmukh
    Sungduk Hong
    Yuan Dai
    Ashkan Behnam
    Feifei Lian
    Eric Pop
    Nano Research, 2016, 9 : 2950 - 2959
  • [2] Sub-15 nm Nanowires Enabled by Cryo Pulsed Self-Aligned Nanotrench Ablation on Carbon Nanotubes
    Deshmukh, Sanchit
    Lian, Feifei
    Yalon, Eilam
    Pitner, Gregory
    Wang, H. -S. Philip
    Pop, Eric
    2017 IEEE 17TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2017, : 489 - 490
  • [3] Fabrication of sub-20 nm patterns using dopamine chemistry in self-aligned double patterning
    Li, Yinyong
    Choi, Jaewon
    Sun, Zhiwei
    Russell, Thomas P.
    Carter, Kenneth R.
    NANOSCALE, 2018, 10 (44) : 20779 - 20784
  • [4] Self-aligned double patterning for active trim contacts with anisotropic pattern pitches in sub-20 nm dynamic random access memories
    Lee, Kiseok
    Kim, Dongoh
    Yoon, Chansic
    Park, Taejin
    Han, Sunghee
    Hwang, Yoosang
    Lee, Kyupil
    Kang, Hokyu
    Kim, Hyoungsub
    JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, 2019, 18 (04):
  • [5] Design consideration of self-aligned recessed channel (RC) devices in sub-100 nm CMOS technology
    Chung, DY
    Lee, JH
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2000, 37 (05) : 617 - 623
  • [6] Probing magnetic properties of STT-MRAM devices down to sub-20 nm using Spin-Torque FMR
    Thomas, Luc
    Jan, Guenole
    Le, Son
    Serrano-Guisan, Santiago
    Lee, Yuan-Jen
    Liu, Huanlong
    Zhu, Jian
    Iwata-Harms, Jodi
    Tong, Ru-Ying
    Patel, Sahil
    Sundar, Vignesh
    Shen, Dongna
    Yang, Yi
    He, Renren
    Haq, Jesmin
    Teng, Zhongjian
    Vinh Lam
    Liu, Paul
    Wang, Yu-Jen
    Zhong, Tom
    Wang, Po-Kang
    2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2017,
  • [7] Probing Self-Heating in RRAM Devices by Sub-100 nm Spatially Resolved Thermometry
    Deshmukh, Sanchit
    Rojo, Miguel Mufioz
    Yalon, Eilam
    Vaziri, Sam
    Pop, Eric
    2018 76TH DEVICE RESEARCH CONFERENCE (DRC), 2018,
  • [8] Large Marginal 2D Self-Aligned Via Patterning for Sub-5nm Technology
    Choi, Suhyeong
    Lee, Jae Uk
    Caballo, Victor M. Blanco
    Debacker, Peter
    Raghavan, Pravccn
    Kim, Ryoung-Han
    Shin, Youngsoo
    DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XI, 2017, 10148
  • [9] Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths
    Yan, Chin-Rung
    Chen, Jone F.
    Lee, Ya-Jui
    Huang, Wei-Shiang
    Huang, Meng-Ju
    Chen, Chih-Yuan
    Lin, Ying-Chia
    Chang, Kuei-Fen
    Chen, Huei-Haurng
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2013, 52 (11)
  • [10] Nanoscale neuroelectrode modification via sub-20 nm silicon nanowires through self-assembly of block copolymers
    Mokarian-Tabari, Parvaneh
    Vallejo-Giraldo, Catalina
    Fernandez-Yague, Marc
    Cummins, Cian
    Morris, Michael A.
    Biggs, Manus J. P.
    JOURNAL OF MATERIALS SCIENCE-MATERIALS IN MEDICINE, 2015, 26 (02)