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- [3] Layout Decomposition of Self-Aligned Double Patterning for 2D Random Logic Patterning DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION V, 2011, 7974
- [4] Fully CMOS Compatible 3D Vertical RRAM with Self-aligned Self-selective Cell Enabling Sub-5nm Scaling 2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2016,
- [5] Self-aligned blocking integration demonstration for critical sub-30-nm pitch Mx level patterning with EUV self-aligned double patterning JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, 2019, 18 (01):
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- [8] Integrated Self-Aligned Multiple Patterning for sub-7nm node Line and Space Scaling ADVANCED ETCH TECHNOLOGY FOR NANOPATTERNING VIII, 2019, 10963
- [9] A Comparative Study of Self-Aligned Quadruple and Sextuple Patterning Techniques for Sub-15nm IC Scaling OPTICAL MICROLITHOGRAPHY XXVI, 2013, 8683
- [10] Self-Aligned Blocking Integration Demonstration for Critical sub 40nm pitch Mx Level Patterning ADVANCED ETCH TECHNOLOGY FOR NANOPATTERNING VI, 2017, 10149