Substrate coupling analysis and simulation for an industrial phase-locked loop

被引：0

作者：

Welch, RJ ^{[1
]}

Yang, AT ^{[1
]}

机构：

[1] USAF, Res Lab, Electron Device Div, Av Directorate, Dayton, OH 45433 USA

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Current injected into the common chip substrate from fast-switching digital devices can affect the operation of sensitive analog circuits in mixed signal designs. An industrial Phase-Locked Loop(PLL) is analyzed with the non-ideal substrate modeled to show the effects of substrate coupling. Detailed simulation results strongly correlate to the measured circuit jitter. Additional results show that well guard structures should not be used and the effectiveness of ohmic guarding structures depends on number, location in the layout, and the bias scheme.

引用

页码：E94 / E97

页数：4

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